1. Field of the Invention
The present invention relates to output buffer circuits. In particular, it relates to output buffer circuits with current-sourcing and current-sinking edge-rate control. More particularly, it relates to buffers with edge-rate control sufficient to significantly increase data-transmission speeds for a wide range of transmission line (bus) impedance presented to the buffers' current-sourcing/sinking node. Specifically, the present invention produces a high-current-capacity, edge-rate-controlled output buffer which maintains edge rates within a narrow temporal range, irrespective of bus load. Furthermore, the present invention accomplishes such edge-rate control with little or no increase in output capacitance or load dependence and with a definite decrease in power dissipation, cross-talk, and EMI in comparison with comparable current-capacity output buffer circuits lacking edge-rate control. Most particularly, the present invention relates to TTL-compatible output buffer circuits capable of driving buses to logic-high and logic-low levels with sufficient current capacity to ensure "incident wave switching" over a wide range of bus impedance and with very favorable output capacitance, power dissipation and noise.
2. Description of the Prior Art
The prior art consists of TTL-compatible output buffers lacking edge-rate control. Buffers lacking such control can effect H.fwdarw.L and L.fwdarw.H transitions at their current sourcing/sinking output nodes which are very short compared with the other factors determining total propagation time between buffer input and buffer output. Indeed, these transitions are too fast in the sense that they give rise to various effects deleterious to efficient data transfer, effects including electromagnetic interference (EMI), "cross talk" between circuits, and output ringing. Because of these consequences of very short H.revreaction.L switching times, increasingly narrow specifications and emerging standards set out narrow "windows" within which a buffer's output edge rates--rising and falling--must fall for a specified wide range of bus impedances. In addition, these edge rate specifications must be met over the entire operating temperature range--generally, -55.degree. to +125.degree. C.--and must be stable in the face of power supply fluctuations.
Solutions of the problem involving a straightforward lengthening of the transition times by, for example, introducing more capacitance on the output node, are precluded, since such an approach makes the buffer prone to overly long transitions in the presence of certain commonly-occurring load conditions. Indeed, once circuitry is introduced to lengthen the transition times, the edge rate displays a dependence on output load that it did not display previously. Therefore, any design changes directed at achieving a controlled edge rate must also address the problem of load dependence. Stated differently, any implementation of a lengthened transition time at the output node must provide for a high current capacity at those lengthened times, especially for the H.fwdarw.L shift. Addressing this aspect of the design problem by simply installing larger output transistors will not work. With MOS pulldown transistors, ensuring high current capacity up to the high end of the specified temperature range requires very large transistors and hence very large capacitances. Very large capacitance at each output node attached to the bus means that an even higher pulldown current capacity is needed, and so forth. With bipolar pulldown transistors, on the other hand, the pulldown circuit must provide for a very high current capacity at room temperature in order to meet the current capacity requirement at the lower end of the temperature range where the bipolar transistor current capacity falls off significantly. Since power dissipation in bipolar transistors is proportional to current, meeting the tighter edge-rate specifications with bipolar pulldown transistors requires a power dissipation level inconsistent with the ever more densely-packed integrated circuitry being designed.
Therefore, what is needed is a TTL-compatible output buffer that incorporates affirmative edge rate control so that the transition waveforms are held within narrow limits over a wide load impedance range, in particular a control which slows down transition times while maintaining sufficient load independence. What is also needed is that such a buffer satisfies these conditions over a broad temperature range-from -55.degree. to +125.degree. C. and that it do this with no increase in buffer output capacitance or power dissipation. The same is true of the edge rate constancy in the face of power supply voltage fluctuations. Finally, what is needed is a buffer design ensuring that these characteristics are maintained independent of normal manufacturing process variations.